Ion microtrap assembly and method of making of making such an assembly

Abstract

An ion-trap chip carrier () comprises a generally planar carrier substrate, the substrate having a front surface, a rear surface, and a chip receptacle. A chip support () is disposed in the chip receptacle of the carrier substrate, the chip support including at least one generally planar flange () extending in or generally parallel to a plane of the carrier substrate, and at least one aperture therein. The chip support comprises a chip receiving zone. The at least one chip support includes at least one front facing electrical terminal () in the chip receiving zone, for coupling to a rear facing terminal of an ion-trap chip (). At least one front facing wire bonding terminal () is electrically coupled to the at least one front facing electrical terminal (), the at least one front facing wire bonding terminal being disposed outside of the chip receiving zone. A chip () is fitted to the carrier () in the chip receiving zone with its rear facing electrical terminals in alignment with the front facing electrical terminals () in the chip receiving zone and electrically connected through the at least one front facing wire bonding terminal, to be wire bonded from the front face of the carrier (). Gold bump studs or pads () connect the rear facing chip terminals with the front facing carrier terminals () and provide both mechanical and electrical connection between the two.