The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 24, 2026

Filed:

Sep. 27, 2022
Applicant:

Nxp B.v., Eindhoven, NL;

Inventors:

Tsung Nan Lo, Taoyuan City, TW;

Antonio Aguinaldo Marquez Macatangay, Sta. Rosa, PH;

Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 24/73 (2013.01); H01L 24/13 (2013.01); H01L 2224/13006 (2013.01); H01L 2224/13014 (2013.01); H01L 2224/2101 (2013.01); H01L 2224/2105 (2013.01); H01L 2224/211 (2013.01); H01L 2224/214 (2013.01); H01L 2224/215 (2013.01); H01L 2224/24991 (2013.01); H01L 2224/73101 (2013.01); H01L 2924/35121 (2013.01);
Abstract

A method of manufacturing a semiconductor device is provided. The method includes forming a redistribution layer (RDL) over a semiconductor die, a portion of the RDL contacting a die pad of the semiconductor die. A non-conductive layer is formed over the RDL. An opening in the non-conductive layer is formed exposing a portion of the RDL. A plurality of plateau regions is formed in the non-conductive layer. A cavity region in the non-conductive layer separates each plateau region of the plurality of plateau regions. A metal layer is deposited over the non-conductive layer and exposed portion of the RDL and etched to expose the plurality of plateau regions through the metal layer. The cavity region remains substantially filled by a portion of the metal layer.


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