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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12588351 B1

PDFFull Text
Date of Patent:
Mar. 24, 2026

Filed:

Dec. 08, 2021

Electronic device and method for manufacturing electronic device

Applicant:

Sony Semiconductor Solutions Corporation, Kanagawa, JP;

Inventors:

Hitoshi Tsuno, Kanagawa, JP;

Hideaki Togashi, Kanagawa, JP;

Tomohiro Ohkubo, Kanagawa, JP;

Masayuki Kurita, Kanagawa, JP;

Syuto Tamura, Kanagawa, JP;

Nobuhiro Kawai, Kanagawa, JP;

Tomoki Hiramatsu, Kanagawa, JP;

Masahiro Joei, Kanagawa, JP;

Kenichi Murata, Kanagawa, JP;

Hideki Tsujiai, Kanagawa, JP;

Tetsuro Takada, Kanagawa, JP;

Assignee:

SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa, JP;

Attorney:

CHIP LAW GROUP

Primary Examiner:

Stanley Tso

Int. Cl.
CPC ...
H10K 39/38 (2023.01); H10K 39/00 (2023.01); H10K 39/32 (2023.01);
U.S. Cl.
CPC ...
H10K 39/38 (2023.02); H10K 39/32 (2023.02); H10K 39/401 (2023.02);
Abstract

Light reduction in a wiring part connected to an optical device of an electronic device including the optical device is prevented. The electronic device includes an insulating layer, an interlayer connection wiring, and an upper layer wiring. The insulating layer is disposed adjacent to the lower layer wiring and includes a through hole. The interlayer connection wiring is a transparent wiring that is connected to the lower layer wiring in the through hole and is formed into a shape extending to a surface side of the insulating layer. The upper layer wiring is a transparent wiring that is stacked and connected to the interlayer connection wiring extending to the surface side of the insulating layer.

Find Patent Forward Citations

Tsuno, Hitoshi. (2026). Electronic device and method for manufacturing electronic device (U.S. Patent No. 12588351). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12588351

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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