The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 24, 2026

Filed:

Jul. 29, 2021
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Sungmin Kim, Incheon, KR;

Daewon Ha, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/49 (2006.01); H01L 21/02 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 64/66 (2025.01);
U.S. Cl.
CPC ...
H10D 64/671 (2025.01); H01L 21/0259 (2013.01); H10D 30/031 (2025.01); H10D 30/6713 (2025.01); H10D 30/6735 (2025.01); H10D 30/6739 (2025.01); H10D 30/6757 (2025.01); H10D 62/118 (2025.01); H10D 64/017 (2025.01); H10D 64/018 (2025.01);
Abstract

A semiconductor device includes a plurality of active regions on a substrate. A gate electrode is on, and intersects, the active regions. A plurality of source/drain regions are on the active regions, such that the source/drain regions are adjacent to opposite sides of the gate electrode and the gate electrode is between the source/drain regions. A separation structure is between adjacent source/drain regions. The separation structure includes an insulating pattern and a spacer layer. The insulating pattern includes first and second side surfaces that are opposite side surfaces of the insulating pattern and are adjacent to separate, respective source/drain regions. The spacer layer is on the first and second side surfaces. An uppermost end of the insulating pattern is farther from a lower surface of the substrate than a first upper surface of the spacer layer that is adjacent to the first and second side surfaces.


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