The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 24, 2026

Filed:

Apr. 02, 2024
Applicant:

Unisantis Electronics Singapore Pte. Ltd., Singapore, SG;

Inventors:

Masakazu Kakumu, Chiyoda-ku, JP;

Koji Sakui, Chiyoda-ku, JP;

Nozomu Harada, Chiyoda-ku, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 12/00 (2023.01); G11C 11/404 (2006.01); G11C 11/4096 (2006.01);
U.S. Cl.
CPC ...
H10B 12/20 (2023.02); G11C 11/404 (2013.01); G11C 11/4096 (2013.01);
Abstract

Provided is a memory semiconductor device including an access transistor, in which an n-type semiconductor layer is formed on a p-type semiconductor region provided on a substrate; a first p-type semiconductor layer that has a columnar shape exists in a vertical direction from a portion of the n-type semiconductor layer; an insulating layer that covers a portion of the first p-type semiconductor layer and a portion of the n-type semiconductor layer exists; in contact therewith, a first gate insulating layer contacts the first p-type semiconductor layer; in contact with the first gate insulating layer, a first gate conductive layer exists; a second p-type semiconductor layer whose surface is recessed exists on the first p-type semiconductor layer; a second gate insulating layer and a second gate conductive layer exist thereabove; and an n+ layer is provided on both sides thereof.


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