Method of fabricating semiconductor memory device including capping layer

Abstract

Disclosed are semiconductor memory devices and their fabrication methods. The method comprises providing a substrate including a cell array region and a boundary region, forming a device isolation layer that defines active sections on an upper portion of the substrate on the cell array region, forming an intermediate layer on the substrate on the boundary region, forming on the substrate an electrode layer that covers the intermediate layer on the boundary region, forming a capping layer on the electrode layer, forming an additional capping pattern including providing a first step difference to the capping layer on the boundary region, and allowing the additional capping pattern, the capping layer, and the electrode layer to proceed an etching process to form bit lines that run across the active sections. During the etching process, the electrode layer is simultaneously exposed on the cell array region and the boundary region.