Multi-chip accelerator architecture for fully homomorphic encryption inference

Abstract

A system for fully homomorphic encryption (FHE) inference includes: a plurality of server modules; an interconnect operatively coupled to the modules and configured to distribute session-initialization data for a large-language-model session; a first plurality of application-specific integrated circuits (ASICs) on one or more of the modules, each configured to perform bootstrapping on ciphertexts during an initiation phase; and a second plurality of ASICs on the modules comprising: bootstrapping circuitry configured to store auxiliary data used for bootstrapping and to perform the bootstrapping operations on the ciphertexts; processing circuitry configured to perform homomorphic arithmetic operations other than bootstrapping; and support circuitry configured to perform functions that support the bootstrapping and processing circuitry.