The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 24, 2026

Filed:

Aug. 30, 2023
Applicants:

Vishal Sarin, saratoga, CA (US);

Biprangshu Saha, bangalore, IN;

Sankha Saha, santa clara, CA (US);

Vikram Kowshik, cupertino, CA (US);

Sang T. Nguyen, union city, CA (US);

Inventors:

Vishal Sarin, saratoga, CA (US);

Biprangshu Saha, bangalore, IN;

Sankha Saha, santa clara, CA (US);

Vikram Kowshik, cupertino, CA (US);

Sang T. Nguyen, union city, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/08 (2006.01); G06G 7/16 (2006.01); G11C 16/04 (2006.01); H03K 7/08 (2006.01); H03M 1/10 (2006.01);
U.S. Cl.
CPC ...
H03M 1/0863 (2013.01); G06G 7/16 (2013.01); G11C 16/0483 (2013.01); H03K 7/08 (2013.01); H03M 1/1057 (2013.01);
Abstract

A matrix multiplication and addition (MAC) operating system is described where different cell currents flowing through different cells in a matrix for different PWM time intervals can be integrated and converted into a numeric value for the cumulative charge. The numeric value of the cumulative charge computed by the ADC is equivalent to MAC operations over multiplicity of cells. The operation is inherently error prone due to parasitic coupling effects from the switching of the memory cells in the array. The presented system minimizes the errors due to parasitic coupling through memory array.


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