The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 24, 2026

Filed:

May. 03, 2024
Applicant:

Apple Inc., Cupertino, CA (US);

Inventors:

Hao-Lin Chiu, Los Gatos, CA (US);

Chin-Wei Lin, San Jose, CA (US);

Shinya Ono, Santa Clara, CA (US);

Kyung Wook Kim, Saratoga, CA (US);

Szu-Hsien Lee, Los Gatos, CA (US);

Pei-En Chang, San Jose, CA (US);

Kwang Soon Park, San Ramon, CA (US);

Assignee:

Apple Inc., Cupertino, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G09G 3/3266 (2016.01); H10D 30/67 (2025.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01);
U.S. Cl.
CPC ...
G09G 3/3266 (2013.01); H10D 86/481 (2025.01); H10D 86/60 (2025.01); G09G 2320/0247 (2013.01); G09G 2330/02 (2013.01); G09G 2354/00 (2013.01); H10D 30/6734 (2025.01);
Abstract

A driver circuit configured to output a control signal to a row of display pixels is provided. The driver circuit can include a first transistor having a drain terminal coupled to a first positive power supply line, a gate terminal, and a source terminal that is coupled to an output port of the driver circuit on which the control signal is generated and a second transistor having a drain terminal coupled to the output port of the driver circuit, a gate terminal, and a source terminal that is coupled to a first ground power supply line. The first and second transistors can be coupled to a plurality of transistors coupled between a second positive power supply line and a second ground power supply line, configured to receive one or more clocks signals, and at least some of which include bottom gate terminals.


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