The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 24, 2026

Filed:

Nov. 07, 2022
Applicant:

Nvidia Corporation, Santa Clara, CA (US);

Inventors:

Rongjian Liang, Austin, TX (US);

Haoxing Ren, Austin, TX (US);

Assignee:

NVIDIA CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/392 (2020.01);
U.S. Cl.
CPC ...
G06F 30/392 (2020.01);
Abstract

Techniques are disclosed herein for designing a circuit. The techniques include receiving a specification for a driver and a plurality of sinks; executing, based on the driver and the plurality of sinks, a machine learning model that predicts at least one of a size, a location, or a delay target of one or more buffers; generating a tree that includes a plurality of nodes representing the driver, the plurality of sinks, and the one or more buffers between the driver and one or more of the sinks; and generating a design of a circuit based on the tree.


Find Patent Forward Citations

Liang, Rongjian. (2026). Techniques for generating designs of circuits that include buffers using machine learning (U.S. Patent No. 12585856). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12585856

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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