The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 24, 2026

Filed:

May. 29, 2023
Applicant:

Netlist, Inc., Irvine, CA (US);

Inventors:

Hyun Lee, Ladera Ranch, CA (US);

Jayesh R. Bhakta, Cerritos, CA (US);

Chi She Chen, Walnut, CA (US);

Jeffery C. Solomon, Irvine, CA (US);

Mario Jesus Martinez, Laguna Niguel, CA (US);

Hao Le, Santa Ana, CA (US);

Soon J. Choi, Irvine, CA (US);

Assignee:

Netlist, Inc., Irvine, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/02 (2006.01); G06F 3/06 (2006.01); G06F 12/06 (2006.01); G06F 12/08 (2016.01); G06F 12/0871 (2016.01); G06F 12/0897 (2016.01); G06F 13/10 (2006.01); G06F 13/28 (2006.01); G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0246 (2013.01); G06F 3/061 (2013.01); G06F 3/068 (2013.01); G06F 3/0685 (2013.01); G06F 12/0638 (2013.01); G06F 12/08 (2013.01); G06F 12/0871 (2013.01); G06F 13/10 (2013.01); G06F 13/28 (2013.01); G11C 7/1072 (2013.01); G06F 3/0656 (2013.01); G06F 3/0688 (2013.01); G06F 12/0897 (2013.01); G06F 2206/1014 (2013.01); G06F 2212/205 (2013.01); G06F 2212/214 (2013.01); G06F 2212/313 (2013.01); G06F 2212/7201 (2013.01); G06F 2212/7208 (2013.01);
Abstract

A memory module comprises dynamic random access memory (DRAM), Flash memory, and a module controller. The module controller is configured to receive data to be transferred from the DRAM to the Flash memory, compute first cyclic redundancy check (CRC) codes for the data, and write the data into the Flash memory. The module controller is further configured to read the data from the Flash memory, compute second CRC codes for the data read from the Flash memory, and transfer the data to the DRAM. The module controller is further configured to compare the second CRC codes with the first CRC codes to determine one or more erroneous data bits in the data read from the Flash memory, read a data segment of the data from the DRAM that include the one or more erroneous data bits, correct the one or more erroneous data bits in the data segment, and write the data segment back into the DRAM.


Find Patent Forward Citations

Loading…