Trace cache access prediction and read enable

Abstract

Disclosed embodiments relate to predicting when a fetch address will hit in a trace cache, e.g., to reduce power consumption when a hit is not predicted. In some embodiments, a processor caches instructions sequentially in a given cache line of instruction cache circuitry. The processor may identify traces of instructions that satisfy one or more criteria and store identified traces in a trace cache. The processor may predict whether a fetch address will hit in the trace cache circuitry. The processor may read in response to a prediction that the fetch address will not hit in the trace cache, instruction data from the instruction cache circuitry and not the trace cache circuitry for the fetch address. The processor may reduce power to (e.g., clock gate) portions of the trace cache circuitry in this scenario.