The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 24, 2026

Filed:

Feb. 09, 2022
Applicant:

Fujitsu Limited, Kawasaki, JP;

Inventors:

Shiro Kamoshida, Kawasaki, JP;

Yuhei Takata, Kawasaki, JP;

Hiroyuki Wada, Kawasaki, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 7/57 (2006.01); G06F 7/487 (2006.01); G06F 7/498 (2006.01);
U.S. Cl.
CPC ...
G06F 7/57 (2013.01); G06F 7/487 (2013.01); G06F 7/4873 (2013.01); G06F 7/4985 (2013.01); G06F 7/4988 (2013.01);
Abstract

An arithmetic processing device includes: a first multiplier circuit configured to calculate a product DY of an approximate value D obtained by approximating a reciprocal 1/Y of a divisor Y; a dividend operation circuit configured to compare a dividend X and the divisor Y, and generate an operation value twice the dividend X or the operation value equal to the dividend X based on a comparison result; a second multiplier circuit configured to calculate a product of the approximate value D and the operation value as an initial value R(0) of a partial remainder R(n); a third multiplier circuit configured to calculate a product DY*q(n) of the product DY and a partial quotient q(n) that is a predetermined number of upper bits of the partial remainder R(n); and a first addition circuit configured to calculate a new partial remainder R(n) by subtracting the product DY*q(n) from the partial remainder R(n).


Find Patent Forward Citations

Kamoshida, Shiro. (2026). Arithmetic processing device and arithmetic method (U.S. Patent No. 12585432). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12585432

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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