The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 24, 2026

Filed:

Sep. 06, 2022
Applicant:

Aeonsemi, Inc., Grand Cayman, KY;

Inventors:

Yunteng Huang, Palo Alto, CA (US);

Adam Eldredge, Frisco, TX (US);

Brian Drost, Hillsboro, OR (US);

Assignee:

Aeonsemi, Inc., Grand Cayman, KY;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/08 (2006.01); G06F 1/10 (2006.01);
U.S. Cl.
CPC ...
G06F 1/08 (2013.01); G06F 1/10 (2013.01);
Abstract

This disclosure provides methods, devices, and systems for generating clock signals. The present implementations more specifically relate to generating multiple clock signals having different frequencies using a single piezoelectric resonator. In some aspects, a clock generator, including a piezoelectric resonator coupled to a voltage amplifier in a feedback network, may be operable in a high-performance mode and a low-power mode. When operating in the high-performance mode, the clock generator may produce a high frequency clock signal and a low frequency clock signal using the same piezoelectric resonator. In some implementations, the high frequency clock signal may be produced by a buffer amplifier coupled to an output of the voltage amplifier and the low frequency clock signal may be produced by a frequency divider coupled to the output of the voltage amplifier. When operating in the low-power mode, the clock generator produces only the low-frequency clock signal via the frequency divider.


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