The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 17, 2026

Filed:

Nov. 23, 2022
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventors:

Tatsuaki Tsukuda, Tokyo, JP;

Tomohiro Nishiyama, Tokyo, JP;

Toshiyuki Hata, Tokyo, JP;

Koichi Hasegawa, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49575 (2013.01); H01L 23/3107 (2013.01); H01L 23/49562 (2013.01); H01L 24/32 (2013.01); H01L 24/40 (2013.01); H01L 24/48 (2013.01); H01L 24/37 (2013.01); H01L 24/45 (2013.01); H01L 24/73 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/37147 (2013.01); H01L 2224/40175 (2013.01); H01L 2224/45144 (2013.01); H01L 2224/45147 (2013.01); H01L 2224/48145 (2013.01); H01L 2224/48245 (2013.01); H01L 2224/73265 (2013.01);
Abstract

The on-resistance of a semiconductor device is reduced. A package structure composing the semiconductor device includes a die pad, a plurality of leads, a first semiconductor chip having a power transistor and mounted on the die pad, and a second semiconductor chip including a control circuit for controlling the power transistor and mounted on the first semiconductor chip. Here, a source pad of the first semiconductor chip is electrically connected to a first lead and a seventh lead of the plurality of leads via a clip made of a material which is copper as a main component, and the width (and cross-sectional area) of the clip is larger than the width (and diameter) of a wire in plan view.


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