The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 17, 2026

Filed:

Apr. 07, 2023
Applicant:

Rockwell Collins, Inc., Cedar Rapids, IA (US);

Inventors:

Orion D. Davies, Cedar Rapids, IA (US);

Haley M. Steffen, Cedar Rapids, IA (US);

Assignee:

Rockwell Collins, Inc., Cedar Rapids, IA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/64 (2006.01); H01L 23/498 (2006.01); H01L 23/552 (2006.01); H01L 25/16 (2023.01);
U.S. Cl.
CPC ...
H01L 25/165 (2013.01); H01L 23/49827 (2013.01); H01L 23/49838 (2013.01); H01L 23/552 (2013.01);
Abstract

A package is described. The package includes a die covered by a lid. The lid maintains a hermetic seal for the die. The package includes high frequency shunt capacitance in parallel with surface-mount capacitors. The high frequency shunt capacitance is formed by interdigital capacitors below the surface-mount capacitors. The interdigital capacitors, the surface-mount capacitors, and the die form a circuit which produces a stable output voltage. The output voltage may remain stable even when subject to noise due to energized particles in space. The package includes solder resist with openings for attaching the surface-mount capacitors to the interdigital capacitors. Advantageously, the interdigital capacitors may achieve high frequency shunt capacitance on the order of nano-farads as part of the frame geometry with minimal increase in package height.


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