The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 17, 2026

Filed:

Apr. 05, 2023
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Juhyeon Kim, Suwon-si, KR;

Ilhwan Kim, Suwon-si, KR;

Sunkyoung Seo, Suwon-si, KR;

Chajea Jo, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/31 (2006.01); H10W 20/20 (2026.01); H10W 20/48 (2026.01); H10W 70/65 (2026.01); H10W 70/685 (2026.01); H10W 74/01 (2026.01); H10W 74/10 (2026.01); H10W 90/00 (2026.01); H10W 72/00 (2026.01); H10W 72/90 (2026.01);
U.S. Cl.
CPC ...
H10W 20/20 (2026.01); H10W 20/48 (2026.01); H10W 70/65 (2026.01); H10W 70/685 (2026.01); H10W 74/016 (2026.01); H10W 74/117 (2026.01); H10W 90/00 (2026.01); H10W 72/856 (2026.01); H10W 72/942 (2026.01); H10W 90/722 (2026.01); H10W 90/724 (2026.01); H10W 90/734 (2026.01);
Abstract

A semiconductor package includes: a first semiconductor chip including first pads; a second semiconductor chip below the first semiconductor chip, the second semiconductor chip including a substrate including a front surface and an opposing rear surface, second pads on the front surface and in contact with the first pads, and through-electrodes electrically connected to the second pads and including protruding portions protruding from the rear surface of the substrate; through-via structures disposed around the second semiconductor chip and in contact with the first pads; a first dielectric layer extending along the rear surface of the substrate and side surfaces of the protruding portions of the through-electrodes; a second dielectric layer below the first dielectric layer and in a space between the protruding portions of the through-electrodes and between the through-via structures; and bump structures below the second dielectric layer and electrically connected to the through-electrodes and the through-via structures.


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