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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12581734 B1

PDFFull Text
Date of Patent:
Mar. 17, 2026

Filed:

Jun. 01, 2021

Display apparatus and electronic apparatus

Applicant:

Samsung Display Co., Ltd., Yongin-si, KR;

Inventors:

Joohee Jeon, Yongin-si, KR;

Bokwang Song, Yongin-si, KR;

Jieun Kim, Yongin-si, KR;

Sanghee Jang, Yongin-si, KR;

Gunhee Kim, Yongin-si, KR;

Sanghwan Cho, Yongin-si, KR;

Assignee:

Samsung Display Co., Ltd., Yongin-si, KR;

Attorney:

Harness, Dickey & Pierce, P.L.C.

Primary Examiner:

Chad M Dicke

Assistant Examiner:

Valerie N Newton

Int. Cl.
CPC ...
H10K 59/126 (2023.01); H10D 86/40 (2025.01); H10K 59/122 (2023.01); H10K 59/123 (2023.01); H10K 59/131 (2023.01); H10K 59/65 (2023.01); H10K 59/80 (2023.01); H10K 102/00 (2023.01);
U.S. Cl.
CPC ...
H10D 86/481 (2025.01); H10K 59/122 (2023.02); H10K 59/131 (2023.02); H10K 59/65 (2023.02); H10K 59/878 (2023.02); H10K 2102/351 (2023.02);
Abstract

A display apparatus includes a substrate, a main pixel circuit, a main display element, an auxiliary pixel circuit, an auxiliary display element, a first bottom metal layer, a second bottom metal layer, and a first barrier layer. The substrate includes a main display area and a component area including a transmission area. The main pixel circuit and the main display element are arranged in the main display area. The auxiliary pixel circuit and the auxiliary display element are arranged in the component area. A first bottom metal layer is arranged between the substrate and the auxiliary pixel circuit in the component area. The second bottom metal layer is arranged between the first bottom metal layer and the auxiliary pixel circuit in the component area. The first barrier layer is arranged between the first bottom metal layer and the second bottom metal layer.

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