The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 17, 2026

Filed:

Feb. 17, 2023
Applicant:

Macom Technology Solutions Holdings, Inc., Lowell, MA (US);

Inventors:

Douglas Carlson, Lowell, MA (US);

Timothy E. Boles, Tyngsboro, MA (US);

Wayne Mack Struble, Franklin, MA (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10D 84/80 (2025.01); H01L 21/762 (2006.01); H01L 23/66 (2006.01); H10D 84/01 (2025.01); H10D 84/08 (2025.01);
U.S. Cl.
CPC ...
H10D 84/811 (2025.01); H01L 21/76224 (2013.01); H01L 23/66 (2013.01); H10D 84/01 (2025.01); H10D 84/08 (2025.01); H01L 2223/6672 (2013.01); H01L 2223/6683 (2013.01);
Abstract

Various methods of forming integrated circuits formed using gallium nitride and other materials are described. An example method includes forming a first integrated device over a first semiconductor structure in a first region of the integrated circuit, forming a second integrated device over a second semiconductor structure in a second region of the integrated circuit, etching a cavity in a third region of the of the integrated circuit located between the first region and the second region, filling the cavity with an insulating material, and forming a passive component over the insulating material in the third region of the integrated circuit. In other aspects, the method can include grinding a back side of a semiconductor substrate of the integrated circuit to electrically isolate the first semiconductor structure from the second semiconductor structure and, after the grinding, forming a ground plane over the back side of the semiconductor substrate.


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