The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 17, 2026

Filed:

Jun. 16, 2023
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventors:

Yudai Higa, Tokyo, JP;

Atsushi Sakai, Tokyo, JP;

Yotaro Goto, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 84/03 (2025.01); H10D 84/01 (2025.01); H10D 84/83 (2025.01);
U.S. Cl.
CPC ...
H10D 84/038 (2025.01); H10D 84/0149 (2025.01); H10D 84/0151 (2025.01); H10D 84/83 (2025.01);
Abstract

A semiconductor device includes a cell region in which MISFETs are formed, and a peripheral region surrounding the cell region in plan view. In the cell region and the peripheral region, an n-type impurity region is formed in a semiconductor substrate. In the semiconductor substrate, an element isolation portion, a p-type impurity region, and an n-type impurity region are formed in the peripheral region so as to surround the cell region in plan view. A p-type impurity region and an n-type impurity region are formed in the semiconductor substrate in the cell region so as to contact the impurity region. The element isolation portion is located in the impurity region and is spaced apart from a junction interface between the impurity region and the impurity region.


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