The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 17, 2026
Filed:
Apr. 28, 2023
Applicant:
Texas Instruments Incorporated, Dallas, TX (US);
Inventor:
Manoj Mehrotra, Plano, TX (US);
Assignee:
TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US);
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10D 84/01 (2025.01); H01L 21/02 (2006.01); H10D 30/69 (2025.01); H10D 62/13 (2025.01); H10D 62/822 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01);
U.S. Cl.
CPC ...
H10D 84/017 (2025.01); H01L 21/02529 (2013.01); H01L 21/02532 (2013.01); H10D 30/797 (2025.01); H10D 62/151 (2025.01); H10D 62/822 (2025.01); H10D 84/0184 (2025.01); H10D 84/038 (2025.01); H10D 84/85 (2025.01);
Abstract
Transistors with raised source/drain structures and methods of making the transistors are described. A method for making such transistors includes forming a first gate and a second gate on a substrate, forming a p-doped region adjacent the first gate, and forming an n-doped region adjacent the second gate. The method further includes forming a silicon germanium (SiGe) region in a portion of the p-doped region. Subsequently, the method simultaneously forms raised source-drain structures over the SiGe region and on the n-doped region.