The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 17, 2026

Filed:

Aug. 15, 2022
Applicant:

Hangzhou Silicon-magic Semiconductor Technology Co., Ltd., Hangzhou City, CN;

Inventors:

Jiakun Wang, Hangzhou City, CN;

Bing Wu, Zhejiang City, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/01 (2025.01); H01L 21/265 (2006.01); H01L 21/266 (2006.01); H10D 30/66 (2025.01); H10D 62/17 (2025.01); H10D 64/00 (2025.01); H10D 64/01 (2025.01);
U.S. Cl.
CPC ...
H10D 30/0297 (2025.01); H01L 21/26513 (2013.01); H01L 21/266 (2013.01); H10D 30/668 (2025.01); H10D 62/393 (2025.01); H10D 64/01 (2025.01); H10D 64/117 (2025.01);
Abstract

Disclosed is a split-gate power MOS device and a manufacturing method thereof. The method comprises: forming a trench in an epitaxial layer on a substrate; forming a first insulation layer on a surface of the epitaxial layer and in the trench; filling a cavity with polycrystalline silicon, performing back-etching; performing spin-coating on the first gate conductor layer to form a second insulation layer; forming a mask on the second insulation layer, removing a portion of the first insulation layer, to expose an upper portion of the trench; forming a gate oxide layer on a sidewall of the upper portion of the trench and the surface of the epitaxial layer; and forming a second gate conductor layer in the upper portion of the trench. According to the present disclosure, voltage withstand and electric leakage between the first gate conductor layer and the second gate conductor layer are reduced.


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