The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 17, 2026

Filed:

Apr. 28, 2022
Applicant:

Institute of Microelectronics, Chinese Academy of Sciences, Beijing, CN;

Inventor:

Huilong Zhu, Poughkeepsie, NY (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 30/01 (2025.01); H10D 30/63 (2025.01); H10D 62/13 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01);
U.S. Cl.
CPC ...
H10D 30/025 (2025.01); H10D 30/63 (2025.01); H10D 62/151 (2025.01); H10D 84/0128 (2025.01); H10D 84/013 (2025.01); H10D 84/038 (2025.01);
Abstract

Provided are a semiconductor device, a method of manufacturing the semiconductor device, and an electronic apparatus including the device. According to the embodiments, the semiconductor device may include: an active region extending substantially in a vertical direction on a substrate; a gate stack formed around at least a portion of an outer periphery of a middle section of the active region in the vertical direction, wherein the active region comprises a channel region opposite to the gate stack, and a first source/drain region and a second source/drain region located on two opposite sides of the channel region in the vertical direction; a first spacer located between a conductor layer of the gate stack and the first source/drain region, and a second spacer located between the conductor layer of the gate stack and the second source/drain region.


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