Method of fabricating a 3d nand flash memory with increased data retention capability

Abstract

A 3D NAND flash memory device and fabricating method thereof, comprises: First, a semiconductor substrate layer is provided, wherein cell isolation structures, channel structures and source lead-out spaces are formed on the semiconductor substrate layer, with the cell isolation structures including cell isolation layers and memory cell-occupied spaces. First dielectric layers and second dielectric layers are sequentially deposited, the first dielectric layer covering at least an exposed surface of the cell isolation structure. The second dielectric layers are then etched to remove all of the second dielectric layers on the side surface and at least part of the second dielectric layers on the second surface, and all of the second dielectric layers on the first surface is retained, with the remaining second dielectric layer forming at least one electron capture layer for memory cell structures. The memory cell structures and electrode structures for the flash memory device are finally fabricated.