The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 17, 2026

Filed:

May. 02, 2023
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Woo Jun Park, Suwon-si, KR;

Kyung Hyun Kim, Suwon-si, KR;

Kun-Woo Park, Suwon-si, KR;

Jun-Youl Yang, Suwon-si, KR;

Dong Woo Lee, Suwon-si, KR;

Sang Hyuk Hong, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10B 43/27 (2023.01); H01L 25/065 (2023.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 41/40 (2023.01); H10B 43/10 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01); H10B 80/00 (2023.01);
U.S. Cl.
CPC ...
H10B 43/27 (2023.02); H01L 25/0652 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 41/40 (2023.02); H10B 43/10 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02); H10B 80/00 (2023.02);
Abstract

A non-volatile memory device comprises a substrate, a mold structure that includes gate electrodes stacked on the substrate and mold insulating layers alternately stacked with the gate electrodes, a cell contact on the substrate, wherein the cell contact is electrically connected to a selection gate electrode of the gate electrodes and is not electrically connected to a non-selection gate electrode of the gate electrodes, an insulating ring on the substrate, wherein the insulating ring is between the non-selection gate electrode and a sidewall of the cell contact and is in contact with the non-selection gate electrode, and a high dielectric constant layer between respective ones of the gate electrodes and the mold insulating layers, wherein the insulating ring includes a first portion that overlaps the high dielectric constant layer in a vertical direction, and a second portion that does not overlap the high dielectric constant layer in the vertical direction.


Find Patent Forward Citations

Quick Actions:

Park, Woo. (2026). Non-volatile memory devices and electronic systems including the same (U.S. Patent No. 12581650). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12581650

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