The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 17, 2026

Filed:

May. 24, 2024
Applicant:

Airoha Technology Corp., Hsinchu City, TW;

Inventors:

Wei-Chen Shen, Hsinchu City, TW;

Tzung-Hung Kang, Kaohsiung City, TW;

Assignee:

Airoha Technology Corp., Hsinchu City, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 3/00 (2006.01); H03M 3/04 (2006.01);
U.S. Cl.
CPC ...
H03M 3/04 (2013.01);
Abstract

A differential successive approximation register (SAR) analog-to-digital converter (ADC) includes a comparator circuit, a sampling circuit, a first capacitive digital-to-analog converter (DAC), a second capacitive DAC, a SAR logic circuit, and a common-mode voltage control circuit. The sampling circuit samples a differential voltage input to generate and output a differential comparator input to the comparator circuit during a sample phase of the differential SAR ADC. The first and second capacitive DACs are coupled to a non-inverting input terminal and an inverting input terminal of the comparator circuit, respectively. The SAR logic circuit controls the first and second capacitive DACs during a SAR phase of the differential SAR ADC. The common-mode voltage control circuit dynamically adjusts an input common-mode voltage of the comparator circuit, wherein the input common-mode voltage of the comparator circuit has different voltage levels during the sample phase and the SAR phase.


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