Power optimized signal chain for low offset drift

Abstract

Described herein are techniques that improve efficiency of analog-to-digital conversion circuits by reducing idling time, during which the ADC circuit is not converting an analog signal to a digital representation, which reduces associated power consumption from keeping the ADC circuit running during idling time. In some embodiments, chop circuits may be used in combination with a plurality of track-and-hold circuits to acquire one polarity of an input signal and convert another polarity of the input signal during a same sampling period. A chop circuit may be configured to alternate between generating a first polarity of the input signal and a second polarity of the input signal. A first T/H circuit may be configured to acquire one polarity of the input signal from the chop circuit while a second T/H circuit provides another polarity of the input signal, previously acquired from the chop circuit, to an ADC for conversion.