The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 17, 2026

Filed:

Nov. 29, 2023
Applicant:

Infineon Technologies Austria Ag, Villach, AT;

Inventors:

Ching Tiu Hsu, Villach, AT;

Tin Chee Chan, Munich, DE;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/0185 (2006.01); H03K 3/012 (2006.01); H03K 3/356 (2006.01);
U.S. Cl.
CPC ...
H03K 19/018521 (2013.01); H03K 3/012 (2013.01); H03K 3/356113 (2013.01);
Abstract

A level shifter includes: a low voltage domain configured to output non-overlapping first and second current pulses based on opposite edges of a logic input signal; and a high voltage domain comprising a latch and a current mirror circuit configured to mirror the non-overlapping first and second current pulses such that the latch is set when the first current pulse is active and reset when the second current pulse is active. The current mirror circuit includes a first mirroring path for the first current pulse and a second mirroring path for the second current pulse. The level shifter has a common mode slew current that is added to the non-overlapping first and second current pulses. The first mirroring path and the second mirroring path are cross-coupled such that the common mode slew current is reduced or cancelled before the non-overlapping first and second current pulses are input to the latch.


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