Block selection circuit controlling series connected pass transistors and flash memory including the same

Abstract

A flash memory includes a memory block connected to word lines, an address decoder that selects one or more of the word lines, a first pass transistor connected to the address decoder, a second pass transistor connected in series with the first pass transistor and connected to one word line among the word lines, a first driver circuit that controls a gate voltage of the first pass transistor based on a first enable signal, and a second driver circuit that controls a gate voltage of the second pass transistor based on a second enable signal. Based on the memory block being an unselected memory block during an erase operation, the first driver circuit controls the first pass transistor to be in a floating state, the second driver circuit controls a power voltage to be provided to a gate of the second pass transistor.