Scan register circuit performing fail bit count operation or position search operation and memory device including the same

Abstract

A memory device includes a memory cell array configured to store data, a page buffer circuit configured to store data in the memory cell array or read data stored in the memory cell array, and a scan register circuit configured to receive a pass/fail result of data from the page buffer circuit and store the pass/fail result in a plurality of scan registers. The scan register circuit obtains information about the scan register where the fail result is stored through a scan operation, and uses the information about the scan register where the fail result is stored to determine the number of fail bits and/or a position index indicating the position of the fail bits according to the operation mode.