Dynamic random-access memory (dram) efficiency calculation and utilization of last level cache (llc)

Abstract

Various embodiments include systems and methods for improving Dynamic Random-Access Memory (DRAM) efficiency and Last Level Cache (LLC) utilization. A computing system may be configured to dynamically adjust DRAM efficiency calculations based on multiple system metrics and conditions (e.g., DDR frequency, density, refresh rates, etc.) for more accurate frequency settings and improved power consumption. The computing system may use a multi-stage approach that includes memory and cache allocation, bandwidth management, and frequency settings. The computing system may fine-tune the DRAM efficiency calculations based on various other factors (e.g., cache miss rates, power consumption, etc.), dynamically modify operational parameters (e.g., DDR frequencies, etc.) in response to specific events or computational tasks, and work in tandem with other system components (e.g., a Last-Level Cache Controller (LLCC), etc.) to improve resource allocation.