The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 17, 2026

Filed:

Jul. 17, 2023
Applicant:

Nvidia Corporation, Santa Clara, CA (US);

Inventors:

Shantanu Sarangi, Saratgoa, CA (US);

Milind Sonawane, Santa Clara, CA (US);

Alex Hsu, New Taipei, TW;

Sailendra Chadalavada, Saratoga, CA (US);

Nitin Yogi, Milpitas, CA (US);

Nithin Valentine, San Jose, CA (US);

Assignee:

NVIDIA CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/34 (2006.01); G01R 31/317 (2006.01); G01R 31/3183 (2006.01);
U.S. Cl.
CPC ...
G06F 11/3457 (2013.01); G01R 31/31721 (2013.01); G01R 31/3183 (2013.01);
Abstract

Systems and methods are disclosed that relate to applications and platforms for performing in-system testing for autonomous or semi-autonomous systems and applications. In some embodiments, resources of a computing system may be grouped into one or more subsets of system elements (e.g., 'a chiplet') and may be configured to be controlled via an associated local controller, which may enable and/or disable the chiplet as targeted. In embodiments, the local controllers may receive instructions from a central controller and, via the enabling and/or disabling of the chiplets, may maintain a number of resources consumed during system testing within a threshold. As a result, the system may be configured to perform system testing without additional resources and/or without redirecting resources that may be intended for other operations.


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