The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 17, 2026
Filed:
Jan. 20, 2020
Ntt, Inc., Tokyo, JP;
Dai Ikarashi, Musashino, JP;
NTT, Inc., Tokyo, JP;
Abstract
A flag sequence generator () generates {x}, . . . , {x} indicating a msb of a. A bit sequence generator () calculates {y}:={x} XOR {x} to generate {y}, . . . , {y}. A flag calculator () calculates an exclusive logical sum of all {x} to calculate [r] for each odd j. A public value multiplier setting-unit () sets r' that becomes √2 when λ is an odd and 1 when λ is an even. A normalization multiplier generator () bit-connects {y}, . . . to generate [c′]. A normalization multiplier generator () bit-connects {x}, . . . to generate [c]. A normalizer () calculates [b]:=[a][c]. A square root calculator () calculates [w]:=[√b]*(r′/√2) when r=1, and [w′]:=[√b]*r′ when r=0. An inverse normalizer () calculates [w][c′] and performs λ′ bits right-shift.