The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 17, 2026

Filed:

Sep. 15, 2023
Applicant:

Apple Inc., Cupertino, CA (US);

Inventors:

John G. Dorsey, San Francisco, CA (US);

Bryan R. Hinch, Campbell, CA (US);

Ronit Banerjee, Mountain View, CA (US);

Karthic A. Palaniappan, Cupertino, CA (US);

Assignee:

Apple Inc., Cupertino, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/00 (2006.01); G06F 1/28 (2006.01);
U.S. Cl.
CPC ...
G06F 1/28 (2013.01);
Abstract

Some embodiments include a system, apparatus, method, and computer program product for memory hierarchy power management. Some embodiments include a performance controller that balances memory hierarchy power and compute power to maintain package-level power efficiency of a systems-on-a-chip (SoC)-memory package. The performance controller can determine a ratio of memory hierarchy power to compute agent power, compare the ratio against a threshold value, and based on the comparison, determine how to manage memory hierarchy power. When the energy costs of the memory hierarchy power are large relative to the energy costs of the compute agent power, some embodiments include changing a performance state of a fabric and/or memory to increase the power efficiency of the overall SoC-memory package, even though a number of memory stall cycles experienced by the compute agent may increase.


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