The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 10, 2026

Filed:

Dec. 02, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventor:

Jiyoung Lee, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49838 (2013.01); H01L 21/4846 (2013.01); H01L 21/56 (2013.01); H01L 23/3128 (2013.01); H01L 23/49822 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 2224/13124 (2013.01); H01L 2224/13139 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/13155 (2013.01); H01L 2224/13166 (2013.01); H01L 2224/16227 (2013.01);
Abstract

A semiconductor package is provided. The semiconductor package includes a first redistribution layer, a first semiconductor chip disposed on the first redistribution layer, a molding layer disposed on the first redistribution layer to cover a side surface of the first semiconductor chip, a second redistribution layer disposed on the molding layer, and a connecting pillar disposed to penetrate the molding layer and configured to connect the first redistribution layer to the second redistribution layer, the connecting pillar including a lower area having a first width in a first direction parallel to an upper surface of the first semiconductor chip and an upper area integrally connected to the lower area and having a second width that is less than the first width in the first direction.


Find Patent Forward Citations

Lee, Jiyoung. (2026). Semiconductor packages and method of manufacturing the same (U.S. Patent No. 12575435). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12575435

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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