The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 10, 2026

Filed:

Mar. 22, 2023
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventors:

Kodai Ozawa, Tokyo, JP;

Sho Nakanishi, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/485 (2006.01); H01L 23/00 (2006.01); H01L 23/495 (2006.01); H10D 62/10 (2025.01);
U.S. Cl.
CPC ...
H01L 24/32 (2013.01); H01L 23/485 (2013.01); H01L 23/49513 (2013.01); H01L 2224/32245 (2013.01); H01L 2924/01023 (2013.01); H01L 2924/01028 (2013.01); H01L 2924/1203 (2013.01); H01L 2924/13055 (2013.01); H01L 2924/1815 (2013.01); H10D 62/102 (2025.01);
Abstract

A semiconductor device includes a lead, a semiconductor substrate, a back-surface electrode provided between the semiconductor substrate and the lead, and a solder layer configured to connect the back-surface electrode and the lead. The back-surface electrode includes a silicide layer formed on a back surface of the semiconductor substrate, a bonding layer formed on the lead, a barrier layer formed on the bonding layer, and a stress relaxation layer formed between the silicide layer and the barrier layer. The stress relaxation layer is made of a first metal film containing aluminum as a main component or a second metal film containing gold, silver, or copper as a main component.


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