The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 10, 2026

Filed:

Mar. 14, 2023
Applicant:

Infineon Technologies Austria Ag, Villach, AT;

Inventors:

Honghai He, Redondo Beach, CA (US);

Robert Haase, San Pedro, CA (US);

Harsh Naik, El Segundo, CA (US);

Timothy Henson, Mount Shasta, CA (US);

Ashita Mirchandani, Rolling Hills Estates, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 84/85 (2025.01); H01L 21/265 (2006.01); H03K 17/687 (2006.01); H10D 30/01 (2025.01); H10D 30/60 (2025.01); H10D 30/65 (2025.01); H10D 30/66 (2025.01); H10D 64/00 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01);
U.S. Cl.
CPC ...
H10D 84/856 (2025.01); H01L 21/26513 (2013.01); H03K 17/6871 (2013.01); H10D 30/022 (2025.01); H10D 30/0289 (2025.01); H10D 30/0297 (2025.01); H10D 30/601 (2025.01); H10D 30/658 (2025.01); H10D 30/668 (2025.01); H10D 64/117 (2025.01); H10D 84/017 (2025.01); H10D 84/0172 (2025.01); H10D 84/038 (2025.01);
Abstract

In an embodiment, a semiconductor device includes a vertical power FET for switching a load current, the power FET including a channel region of a first conductivity type and a first lateral FET and a second lateral FET providing an output stage of gate driver circuitry for driving the power FET. The first lateral FET includes a channel region of the first conductivity type and the second lateral FET includes a channel region of a second conductivity type opposing the first conductivity type. The power FET and the first and second lateral FETs are monolithically integrated into a semiconductor substrate of the first conductivity type and that has a first surface. A drain of the first lateral FET and a source of the second lateral FET are electrically coupled to a gate of the power FET.


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