Multiple gate-all-around semiconductor devices with gate separation

Abstract

A semiconductor memory device includes: a substrate having first and second channel structures extending in a first direction arranged spaced apart in a second direction; a first gate structure disposed on the first channel structure; a second gate structure disposed on the second channel structure; first source/drain regions disposed on opposite sides of the first gate structure; second source/drain regions disposed on opposite sides of the second gate structure; a gate separation pattern disposed between the gate structures to directly contact the gate structures and having an upper surface disposed at a level lower than an upper surface of the gate structures along a third direction; and a gate capping layer disposed on the gate structures and having an extension portion disposed between the gate structures such that the extension portion directly contacts the gate structures, the gate capping layer being connected to the gate separation pattern.