Semiconductor memory device

Abstract

A semiconductor memory device includes a plurality of memory cells arranged on a substrate. Each of the plurality of memory cells may include a first transistor on the substrate and a second transistor on the first transistor. The first transistor may include a first channel region between a first source region and a first drain region, a first gate electrode, and a first gate insulating layer. The second transistor may include a pillar structure having a second drain region, a second channel region and a second source region sequentially stacked on the first gate electrode, a second gate electrode on one side of the second channel region, and a second gate insulating layer between the second channel region and the second gate electrode. the second drain region and the second source region may have a first conductivity type impurity region and a second conductivity type impurity region, respectively.