The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 10, 2026
Filed:
Jan. 10, 2024
Analog Devices, Inc., Wilmington, MA (US);
Shuo Xie, Tempe, AZ (US);
Hio Leong Chao, Tempe, AZ (US);
Ling Su, Chandler, AZ (US);
Xu Wang, Phoenix, AZ (US);
Analog Devices, Inc., Wilmington, MA (US);
Abstract
A transistor assembly with gate current shunting capability includes first field effect transistor (FET), a first pull-up current source, a first pull-down current source, a first switching device, a control circuit, a capacitor, and a second FET. The first FET is an N-channel FET including a first gate, a first drain, and a first source. The first drain is electrically coupled to a first power supply. Each of the pull-up current source and the pull-down current source is electrically coupled to the first gate. The first switching device is electrically coupled in series with the first pull-down current source and is controlled by a first control signal. The control circuit is at least partially powered by a second power supply and generates the first control signal. The capacitor and the second FET collectively shunt current away from the first gate during a pre-power operating state of the transistor assembly.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile