The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 10, 2026

Filed:

Mar. 22, 2022
Applicant:

Qualcomm Technologies, Inc., San Diego, CA (US);

Inventor:

Fabrice Devaux, Lausanne, CH;

Assignee:

Qualcomm Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 11/406 (2006.01); G11C 11/4078 (2006.01); G11C 11/408 (2006.01); G11C 29/52 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4078 (2013.01); G11C 11/40615 (2013.01); G11C 11/40618 (2013.01); G11C 11/408 (2013.01); G11C 29/52 (2013.01);
Abstract

The invention relates to a method for protecting a memory device () from the effect of row hammering. The memory device () comprises a DRAM unit (U) formed by a plurality of memory point matrices (MAT-MATN) subdivided into a plurality of memory blocks (B-BM). The memory device () comprises activation counters (CTR-CTRM) respectively associated with the memory blocks (B-BM). The method comprises the execution, with each activation of a row of a given block (Bi), of a step of incrementing the activation counter (CTRi) associated with the given block (Bi); and the initiation of the preventive refresh of all the rows of the given block (Bi) when the activation counter (CTRi) of this given block (Bi) exceeds a threshold value (Si). The protection method also comprises at least one of the operations aimed at: —including, in the preventive refresh, at least some of the rows of at least one block directly adjacent (Bi+1, Bi−1) to the given block (Bi); —incrementing, during the activation of the row or of certain rows of the given block (Bi), the activation counter (CTRi−1, CTRi+1) of at least one block directly adjacent (Bi−1, Bi+1) to the given block (Bi) and initiating the preventive refresh of all the rows of the adjacent block (Bi−1, Bi+1) when the activation counter (CTRi−1, CTRi+1) associated with this adjacent block (Bi−1, Bi+1) exceeds a threshold value (Si−1, Si+1).


Find Patent Forward Citations

Devaux, Fabrice. (2026). Memory device and method for protecting a memory device from the effect of row hammering (U.S. Patent No. 12573444). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12573444

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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