The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 10, 2026

Filed:

Jan. 07, 2022
Applicant:

Imagination Technologies Limited, Kings Langley, GB;

Inventor:

Xile Yang, Rickmansworth, GB;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06T 15/20 (2011.01); G06T 7/13 (2017.01); G06T 7/507 (2017.01); G06T 7/529 (2017.01); G06T 15/00 (2011.01); G06T 15/04 (2011.01); G06T 15/40 (2011.01); G06T 17/10 (2006.01); G06T 17/20 (2006.01); G06T 19/20 (2011.01);
U.S. Cl.
CPC ...
G06T 15/205 (2013.01); G06T 7/13 (2017.01); G06T 7/507 (2017.01); G06T 7/529 (2017.01); G06T 15/005 (2013.01); G06T 15/04 (2013.01); G06T 15/40 (2013.01); G06T 17/10 (2013.01); G06T 17/205 (2013.01); G06T 19/20 (2013.01); G06T 2200/04 (2013.01); G06T 2200/28 (2013.01); G06T 2207/10004 (2013.01); G06T 2207/10028 (2013.01); G06T 2207/20004 (2013.01); G06T 2207/20192 (2013.01); G06T 2215/16 (2013.01); G06T 2219/2016 (2013.01);
Abstract

A tiling unit assigning primitives to tiles in a graphics processing system which has a rendering space subdivided into a plurality of tiles. Each tile can comprise one or more polygonal region. Mesh logic of the tiling unit can determine that a plurality of primitives form a mesh and can determine whether the mesh entirely covers a region. If the mesh entirely covers the region then a depth threshold for the region can be updated so that subsequent primitives which lie behind the depth threshold are culled (i.e. not included in the display list for a tile). This helps to reduce the number of primitive IDs included in a display list for a tile which reduces the amount of memory used by the display list and reduces the number of primitives which a hidden surface removal (HSR) module needs to fetch to perform HSR on the tile.


Find Patent Forward Citations

Quick Actions:

Yang, Xile. (2026). Assigning primitives to tiles in a graphics processing system (U.S. Patent No. 12573132). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12573132

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