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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12572478 B1

PDFFull Text
Date of Patent:
Mar. 10, 2026

Filed:

May. 09, 2024

Method and apparatus for dual issue multiply instructions

Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Timothy David Anderson, University Park, TX (US);

Mujibur Rahman, Plano, TX (US);

Assignee:

TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US);

Attorneys:

Michael T. Gabrik

Frank D. Cimino

Primary Examiner:

Michael Sun

Int. Cl.
CPC ...
G06F 9/30 (2018.01); G06F 7/24 (2006.01); G06F 7/487 (2006.01); G06F 7/499 (2006.01); G06F 7/53 (2006.01); G06F 7/57 (2006.01); G06F 9/32 (2018.01); G06F 9/345 (2018.01); G06F 9/38 (2018.01); G06F 9/48 (2006.01); G06F 11/00 (2006.01); G06F 11/10 (2006.01); G06F 12/0862 (2016.01); G06F 12/0875 (2016.01); G06F 12/0897 (2016.01); G06F 12/1009 (2016.01); G06F 12/1045 (2016.01); G06F 17/16 (2006.01); H03H 17/06 (2006.01); G06F 15/78 (2006.01);
U.S. Cl.
CPC ...
G06F 12/1045 (2013.01); G06F 7/24 (2013.01); G06F 7/487 (2013.01); G06F 7/4876 (2013.01); G06F 7/49915 (2013.01); G06F 7/53 (2013.01); G06F 7/57 (2013.01); G06F 9/3001 (2013.01); G06F 9/30014 (2013.01); G06F 9/30018 (2013.01); G06F 9/30021 (2013.01); G06F 9/30032 (2013.01); G06F 9/30036 (2013.01); G06F 9/30065 (2013.01); G06F 9/30072 (2013.01); G06F 9/30098 (2013.01); G06F 9/30112 (2013.01); G06F 9/30145 (2013.01); G06F 9/30149 (2013.01); G06F 9/3016 (2013.01); G06F 9/32 (2013.01); G06F 9/345 (2013.01); G06F 9/3802 (2013.01); G06F 9/3818 (2013.01); G06F 9/383 (2013.01); G06F 9/3836 (2013.01); G06F 9/3851 (2013.01); G06F 9/3856 (2023.08); G06F 9/3867 (2013.01); G06F 9/3887 (2013.01); G06F 9/48 (2013.01); G06F 11/00 (2013.01); G06F 11/1048 (2013.01); G06F 12/0862 (2013.01); G06F 12/0875 (2013.01); G06F 12/0897 (2013.01); G06F 12/1009 (2013.01); G06F 17/16 (2013.01); H03H 17/0664 (2013.01); G06F 9/325 (2013.01); G06F 9/381 (2013.01); G06F 9/3822 (2013.01); G06F 11/10 (2013.01); G06F 15/7807 (2013.01); G06F 15/781 (2013.01); G06F 2212/452 (2013.01); G06F 2212/60 (2013.01); G06F 2212/602 (2013.01); G06F 2212/68 (2013.01);
Abstract

Various configurations of processors are provided. In a configuration, the processor comprises first and second multiplication units. The first multiplication unit includes first multiply circuitry including a first set of outputs; and first multiplexing logic coupled to the first set of outputs and configured to generate a first partial sum and a first partial carry. The second multiplication unit includes second multiply circuitry including a second set of outputs; and second multiplexing logic coupled to the second set of outputs and configured to generate a second partial sum and a first partial carry.

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