The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 10, 2026
Filed:
Sep. 23, 2025
Applicant:
Onesta Ip, Llc, Wayne, PA (US);
Inventors:
Skyler J. Saleh, San Diego, CA (US);
Samuel Naffziger, Fort Collins, CO (US);
Milind S. Bhagavat, Wayne, PA (US);
Rahul Agarwal, Wayne, PA (US);
Assignee:
Onesta IP, LLC, Wayne, PA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2016.01); G06F 12/0897 (2016.01); G06F 13/16 (2006.01); G06F 13/40 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0897 (2013.01); G06F 13/1668 (2013.01); G06F 13/4027 (2013.01); G06F 2212/1024 (2013.01);
Abstract
A chiplet system includes a central processing unit (CPU) communicably coupled to a first GPU chiplet of a GPU chiplet array. The GPU chiplet array includes the first GPU chiplet communicably coupled to the CPU via a bus and a second GPU chiplet communicably coupled to the first GPU chiplet via a passive crosslink. The passive crosslink is a passive interposer die dedicated for inter-chiplet communications and partitions systems-on-a-chip (SoC) functionality into smaller functional chiplet groupings.