Semiconductor memory devices with error correction

Abstract

A memory system includes a semiconductor memory device and a memory controller to control the semiconductor memory device. The semiconductor memory device includes a memory cell array that is divided into a plurality of sub array blocks arranged in a first direction and a second direction. The memory controller includes an error correction code (ECC) engine. The ECC engine, in a write operation, generates a parity data by performing an ECC encoding on a user data including a plurality of sub data units, generates a main data by interleaving the sub data units based on mapping information such that two sub data units to be stored in one row of a target sub array block are included in one symbol. The mapping information indicates a mapping relationship between the plurality of sub data units and rows of the target sub array block storing the plurality of sub data units.