The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 10, 2026

Filed:

Dec. 13, 2023
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Nigam Mohan Palo, Hyderabad, IN;

Sagar Kotte, Hyderabad, IN;

Ajeet Tripathi, Satna, IN;

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/32 (2019.01); G06F 1/3206 (2019.01); G06F 1/3287 (2019.01); G06F 1/3296 (2019.01);
U.S. Cl.
CPC ...
G06F 1/3287 (2013.01); G06F 1/3206 (2013.01); G06F 1/3296 (2013.01);
Abstract

Aspects of the disclosure are directed to power management of a processor. In accordance with one aspect, the disclosure is directed towards monitoring a relationship between a performance of a processor and one or more hysteresis levels for generating a hysteresis feedback value based on the relationship; generating a corrected hysteresis level based on the hysteresis feedback value; and adjusting the corrected hysteresis level to generate an adjusted corrected hysteresis level.


Find Patent Forward Citations

Palo, Nigam. (2026). Processor low power mode enhancement (U.S. Patent No. 12572194). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12572194

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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