Systems for and methods for clock calibration adjustment for three-dimensional intergrated circuits (3dic)

Abstract

Clock calibration adjustments are provided. Some embodiments disclosed herein are related to a device. A device can include a first conductive element configured to receive a first signal at a first functional block. The device can include a second conductive element configured to convey the first signal to a second functional block of the device. The device can include a third conductive element to receive a second signal from the second functional block, the second signal varying from the first signal according to a phase-shift. The device can include a first circuit configured to determine the phase-shift between the first signal and the second signal. The device can include a second circuit configured to generate a third signal based on the phase-shift, the first signal, the second signal.