The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 03, 2026
Filed:
Jun. 15, 2022
Google Llc, Mountain View, CA (US);
Georgios Konstadinidis, San Jose, CA (US);
Woon-Seong Kwon, Santa Clara, CA (US);
Jaesik Lee, Santa Clara, CA (US);
Teckgyu Kang, Saratoga, CA (US);
Jin Y. Kim, Mountain View, CA (US);
Sukalpa Biswas, Fremont, CA (US);
Biao He, Sunnyvale, CA (US);
Yujeong Shim, Cupertino, CA (US);
Google LLC, Mountain View, CA (US);
Abstract
A microelectronic system may include a substrate having a first surface, one or more interposers mounted to and electrically connected to the first surface, first and second application specific integrated circuits (ASICs) each at least partially overlying and electrically connected to one of the interposers, a plurality of high-bandwidth memory elements (HBMs) each at least partially overlying and electrically connected to one of the interposers, and an active silicon bridge mounted to and electrically connected to the first surface and providing an electrical connection between the first and second ASICs, the active silicon bridge having active microelectronic devices therein. The microelectronic system may be configured such that the first and second ASICs and the active silicon bridge each have a purely digital CMOS interface therein. A plurality of bumps providing the electrical connection between the ASICs and the active silicon bridge may be configured to receive serial data therethrough.