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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12568741 B1

PDFFull Text
Date of Patent:
Mar. 03, 2026

Filed:

Sep. 12, 2022

Display panel including support substrate bonded to encapsulation substrate and method for fabricating the same

Applicant:

Samsung Display Co., Ltd., Yongin-Si, KR;

Inventors:

Yun Yong Nam, Hwaseong-si, KR;

So Young Koo, Hwaseong-si, KR;

Eok Su Kim, Seoul, KR;

Hyung Jun Kim, Seoul, KR;

Jun Hyung Lim, Seoul, KR;

Kyung Jin Jeon, Incheon, KR;

Assignee:

Samsung Display Co., Ltd., Yongin-si, KR;

Attorney:

Innovation Counsel LLP

Primary Examiner:

Jacob Y Choi

Assistant Examiner:

Grace undefined Cha

Int. Cl.
CPC ...
H10K 59/131 (2023.01); H10K 50/84 (2023.01); H10K 50/844 (2023.01); H10K 59/122 (2023.01); H10K 59/126 (2023.01); H10K 71/00 (2023.01);
U.S. Cl.
CPC ...
H10K 59/131 (2023.02); H10K 50/841 (2023.02); H10K 50/844 (2023.02); H10K 59/122 (2023.02); H10K 59/126 (2023.02); H10K 71/00 (2023.02);
Abstract

The present disclosure relates to a display panel and a method for fabricating the same. According to an embodiment, a method for fabricating a display panel, comprises disposing a circuit array and connection lines on the support substrate, the circuit array disposed in the display area, the connection lines disposed in a non-display area; disposing a via layer on the support substrate; providing a sealing hole surrounding the display area by patterning the via layer; disposing a sealing member surrounding the display area on an encapsulation substrate. In the disposing of the circuit array and the connection lines comprises disposing an active layer overlapping a light shielding member and disposing an etch stopper corresponding to at least a portion of an overlapping area between the sealing hole and the first connecting line part, by patterning a semiconductor material layer on the buffer layer.

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