The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 03, 2026

Filed:

Jul. 27, 2020
Applicant:

Semiconductor Energy Laboratory Co., Ltd., Atsugi, JP;

Inventors:

Naoto Goto, Tochigi, JP;

Naoki Ikezawa, Tochigi, JP;

Masataka Nakada, Tochigi, JP;

Ami Sato, Tochigi, JP;

Chieko Misawa, Utsunomiya, JP;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 30/67 (2025.01); H10D 30/01 (2025.01);
U.S. Cl.
CPC ...
H10D 30/6755 (2025.01); H10D 30/031 (2025.01); H10D 30/6757 (2025.01);
Abstract

A semiconductor device with favorable electrical characteristics is provided. A highly reliable semiconductor device is provided. The semiconductor device includes a semiconductor layer, a first insulating layer over the semiconductor layer, and a conductive layer over the first insulating layer. The semiconductor layer includes a first region, a pair of second regions, a pair of third regions, and a pair of fourth regions. The second regions sandwich the first region, the third regions sandwich the first region and the second regions, and the fourth regions sandwich the first region, the second regions, and the third regions. The first region includes a region overlapping with the first insulating layer and the conductive layer, the second regions and the third regions each include a region overlapping with the first insulating layer and not overlapping with the conductive layer, and the fourth regions overlap with neither the first insulating layer nor the conductive layer. A thickness of the first insulating layer in regions overlapping with the second regions is substantially equal to a thickness of the first insulating layer in a region overlapping with the first region. A thickness of the first insulating layer in regions overlapping with the third regions is smaller than the thickness of the first insulating layer in the regions overlapping with the second regions.


Find Patent Forward Citations

Goto, Naoto. (2026). Semiconductor device and method for manufacturing semiconductor device (U.S. Patent No. 12568654). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12568654

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